This invention relates to address input buffers for use with a random-access memory.
In a dynamic random-access memory, in the read or write mode thereof, the x and y addresses in the random-access memory are gained through decoders, in turn operatively connected with respective address buffers. In the general prior-art design, each buffer has a number of inputs connected therewith, each of which is in a high or low state, with each input controlling the state of a pair of outputs, in turn communicating with the respective decoder. As commonly used, a high input determines a high-low output pair, while a low input determines the reverse, or low-high output pair.
It will be understood that it is highly desirable that such a buffer be compatible with transistor-transistor-logic input, meanwhile being rapid and effective in operation even with a relatively large variation in power supply.
Various designs for use in such environment exhibited certain drawbacks. For example, in certain buffer designs, the buffer speed varies with input level. Also, the input level may affect loading. Additionally, a high peak current may be required for fast buffer output. It is also to be noted that some of these buffer circuits also exhibit sensitivity problems, and require complex clocking schemes.
One known design uses a constant supply voltage as a reference chosen as between the low and high voltage levels of the system. Such a system, while generally effective in performance, includes certain problems. For example, the maintenance of such reference voltage dissipates current which adds to the chip stand-by mode power dissipation. Additionaly, the circuit scheme incorporating this system has been found to be relatively complicated, and it has also been found rather difficult to maintain such reference voltage at a substantially constant level.